Hi Robin,
Thanks for the review. Please find my comment below inline.
> -----Original Message-----
> From: Robin Murphy <robin.murphy@xxxxxxx>
> Sent: Friday, August 28, 2020 12:17 AM
> To: Manish Narani <MNARANI@xxxxxxxxxx>; gregkh@xxxxxxxxxxxxxxxxxxx;
> robh+dt@xxxxxxxxxx; Michal Simek <michals@xxxxxxxxxx>; balbi@xxxxxxxxxx;
> p.zabel@xxxxxxxxxxxxxx
> Cc: devicetree@xxxxxxxxxxxxxxx; linux-usb@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; git <git@xxxxxxxxxx>; linux-arm-
> kernel@xxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH 2/2] usb: dwc3: Add driver for Xilinx platforms
>
> On 2020-08-26 19:44, Manish Narani wrote:
> [...]
> > + /*
> > + * This routes the usb dma traffic to go through CCI path instead
> > + * of reaching DDR directly. This traffic routing is needed to
> > + * make SMMU and CCI work with USB dma.
> > + */
> > + if (of_dma_is_coherent(dev->of_node) || dev->iommu_group) {
> > + reg = readl(priv_data->regs + XLNX_USB_COHERENCY);
> > + reg |= XLNX_USB_COHERENCY_ENABLE;
> > + writel(reg, priv_data->regs + XLNX_USB_COHERENCY);
> > + }
>
> This looks rather suspect - coherency should be based on coherency, not
> on whether an IOMMU group is present. If the device isn't described as
> coherent in the DT, then any SMMU mappings will end up using attributes
> that will downgrade traffic to be non-snooping anyway. And if the SMMU
> is enabled but not translating (e.g. "iommu.passthrough=1") then
> enabling hardware coherency when the DMA layer hasn't been told about it
> can potentially lead to nasty subtle problems and data loss.
May be the description needs to be updated in this. This is not the actual coherency enabling bit, but this is needed when coherency is enabled.
This is a register inside Xilinx USB controller which handles USB (which is in LPD) traffic route switching from LPD (Low Power Domain) to FPD (Full Power Domain) path in the Xilinx SoC in either of the below scenarios:
1. Device is described coherent in DT.
2. SMMU is enabled.
I will update the same in v2.
Thanks,
Manish
