Hi,
On 20-06-08 21:11, Li Jun wrote:
...
> +static int imx8mp_usb_phy_init(struct phy *phy)
> +{
> + struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
> + u32 value;
> +
> + /* USB3.0 PHY signal fsel for 24M ref */
> + value = readl(imx_phy->base + PHY_CTRL0);
> + value &= ~PHY_CTRL0_FSEL_MASK;
> + value |= PHY_CTRL0_FSEL_24M;
> + writel(value, imx_phy->base + PHY_CTRL0);
> +
> + /* Disable alt_clk_en and use internal MPLL clocks */
> + value = readl(imx_phy->base + PHY_CTRL6);
> + value &= ~(PHY_CTRL6_ALT_CLK_SEL | PHY_CTRL6_ALT_CLK_EN);
> + writel(value, imx_phy->base + PHY_CTRL6);
> +
> + value = readl(imx_phy->base + PHY_CTRL1);
> + value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0);
> + value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
> + writel(value, imx_phy->base + PHY_CTRL1);
> +
> + value = readl(imx_phy->base + PHY_CTRL0);
> + value |= PHY_CTRL0_REF_SSP_EN;
> + writel(value, imx_phy->base + PHY_CTRL0);
> +
> + value = readl(imx_phy->base + PHY_CTRL2);
> + value |= PHY_CTRL2_TXENABLEN0 | PHY_CTRL2_OTG_DISABLE;
> + writel(value, imx_phy->base + PHY_CTRL2);
> +
> + udelay(10);
Nit:
Do we need the active wait here or is it also possible to use
usleep_range() here?
> +
> + value = readl(imx_phy->base + PHY_CTRL1);
> + value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
> + writel(value, imx_phy->base + PHY_CTRL1);
> +
> + return 0;
> +}
