Hi Martin,
On Tue, 18 Aug 2020 at 08:33, Anand Moon <linux.amoon@xxxxxxxxx> wrote:
>
> Hi Martin,
>
> Thanks for your review comments .
>
> On Tue, 18 Aug 2020 at 01:06, Martin Blumenstingl
> <martin.blumenstingl@xxxxxxxxxxxxxx> wrote:
> >
> > Hi Anand,
> >
> > thank you for updating this patch!
> >
> > On Mon, Aug 17, 2020 at 12:21 PM Anand Moon <linux.amoon@xxxxxxxxx> wrote:
> > [...]
> > > changes v2
> > > --Fix the missing INT (GPIOA.BIT7) pinctrl.
> > should I also expect an interrupt property somewhere below?
> >
> > > --Fix the missing rtcwakeup.
> > > --Drop the clock not required clock property by the PCF8563 driver.
> > > ---
> > > .../arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts | 13 +++++++++++++
> > > 1 file changed, 13 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
> > > index 34fffa6d859d..f08ae1b337ad 100644
> > > --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
> > > +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
> > > @@ -477,6 +477,19 @@ hdmi_tx_tmds_out: endpoint {
> > > };
> > > };
> > >
> > > +&i2c3 {
> > > + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
> > > + pinctrl-1 = <&tdm_c_din3_a_pins>;
Note: without setting this *pinctrl-1* configuration RTC wake up
feature works as expected.
> > > + pinctrl-names = "default";
> > why is there pinctrl-1 without any corresponding "pinctrl-names" entry?
> > also I'm surprised to see a TDM (audio) related pin function as part
> > of an I2C controller. if this is correct then I'd appreciate a bit
> > information (for example as part of the patch description) why that is
> >
> >
> > Martin
>
> Opps, I could not figure the difference between GPIOA_7 and GPIOAO_7 pins
> I will try to figure out the correct configuration pin for this node.
>
> Best Regards
> -Anand
I see from the schematics [0] odroid-n2_rev0.4_20190307.pdf section S905D2 IO.
Following pin configuration is used for RTC
RTC GPIOAO_7(JTAG_A_TMS//TSIN_A_DIN0//TDMB_FS//TDMB_SLV_FS)
As per the data sheets [1] S922X_Public_Datasheet_V0.2.pdf following
are the pin funtion description.
JTAG_A_TMS DI JTAG Test mode
select input channel A
TSIN_A_DIN0 DI Serial TS input port A data
TDMB_FS DO Frame sync output
of TDM port B (Word clock of I2S)
TDMB_SLV_FS DI Frame sync input of
TDM port B (Word clock of I2S)
But I dont observe this configration is linked to the RTC INT (GPIOAO.BIT7) pin.
Without setting the *pinctrl-1* rtc is getting registeed correcly and
suspend / resume feature is also working correcly see below.
[root@archl-on2e ~]# dmesg | grep rtc
[ 5.269079] rtc-pcf8563 0-0051: registered as rtc0
[ 5.270948] rtc-pcf8563 0-0051: setting system clock to
2020-08-18T04:52:26 UTC (1597726346)
[root@archl-on2e ~]#
[root@archl-on2e ~]#
[root@archl-on2e ~]# rtcwake -s 30 -m mem
rtcwake: assuming RTC uses UTC ...
rtcwake: wakeup from "mem" using /dev/rtc0 at Tue Aug 18 05:06:05 2020
[ 793.341957] PM: suspend entry (deep)
[ 793.342292] Filesystems sync: 0.000 seconds
[ 793.649621] Freezing user space processes ... (elapsed 0.001 seconds) done.
[ 793.652309] OOM killer disabled.
[ 793.655514] Freezing remaining freezable tasks ... (elapsed 0.001
seconds) done.
[ 793.666584] meson8b-dwmac ff3f0000.ethernet eth0: Link is Down
[ 793.686014] sd 0:0:0:0: [sda] Synchronizing SCSI cache
[ 793.778908] Disabling non-boot CPUs ...
[ 793.783712] CPU1: shutdown
[ 793.783845] psci: CPU1 killed (polled 0 ms)
[ 793.795813] CPU2: shutdown
[ 793.795941] psci: CPU2 killed (polled 0 ms)
[ 793.807337] CPU3: shutdown
[ 793.807465] psci: CPU3 killed (polled 0 ms)
[ 793.819110] CPU4: shutdown
[ 793.819235] psci: CPU4 killed (polled 0 ms)
[ 793.833682] CPU5: shutdown
[ 793.834614] psci: CPU5 killed (polled 0 ms)
bl30 get wakeup sources!
process command 00000006
bl30 enter suspend!
Little core clk suspend rate 100000000
Big core clk suspend rate 24000000
store restore gp0 pll
suspend_counter: 1
Enter ddr suspend
ddr suspend time: 16us
alarm=0S
process command 00000001
GPIOA_11/13 off
cec ver:2018/04/19
CEC cfg:0x0000
WAKEUP GPIO cfg:0x00000000
use vddee new table!
kern log_addr:0x00
cec T: 00
err: tx not finish flag
cec reset
Set cec pinmux:0x11
Set cec log_addr:0x10,ADDR0:10
use vddee new table!
exit_reason:0x03
Enter ddr resume
ddr resume time: 124us
store restore gp0 pll
cfg15 3b00000
cfg15 33b00000
Little [ 793.845285] Enabling non-boot CPUs ...
core clk re[ 793.846900] Detected VIPT I-cache on CPU1
[ 793.847250] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[ 793.850966] CPU1 is up
[ 793.858728] Detected VIPT I-cache on CPU2
[ 793.858825] arch_timer: CPU2: Trapping CNTVCT access
[ 793.858851] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
[ 793.860784] cpufreq: cpufreq_online: CPU2: Running at unlisted
freq: 999999 KHz
[ 793.880028] cpufreq: cpufreq_online: CPU2: Unlisted initial
frequency changed to: 1000000 KHz
[ 793.889018] CPU2 is up
[ 793.891578] Detected VIPT I-cache on CPU3
[ 793.891609] arch_timer: CPU3: Trapping CNTVCT access
[ 793.891617] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
[ 793.892276] CPU3 is up
[ 793.909048] Detected VIPT I-cache on CPU4
[ 793.909077] arch_timer: CPU4: Trapping CNTVCT access
[ 793.909084] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
[ 793.909896] CPU4 is up
[ 793.926797] Detected VIPT I-cache on CPU5
[ 793.926827] arch_timer: CPU5: Trapping CNTVCT access
[ 793.926834] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
[ 793.927609] CPU5 is up
sume rate 100000000
Big core clk resume rate 50000000
[ 793.971976] meson8b-dwmac ff3f0000.ethernet eth0: No Safety
Features support found
[ 793.974405] meson8b-dwmac ff3f0000.ethernet eth0: configuring for
phy/rgmii link mode
[root@archl-on2e ~]# dmesg | grep rtc
[ 5.269079] rtc-pcf8563 0-0051: registered as rtc0
[ 5.270948] rtc-pcf8563 0-0051: setting system clock to
2020-08-18T04:52:26 UTC (1597726346)
Schematics [0] https://dn.odroid.com/S922X/ODROID-N2/Schematic/odroid-n2_rev0.4_20190307.pdf
Datasheets [1] https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
Best Regards
-Anand
