This driver adds support for the interrupt controllers
present between the various IP blocks and the ARM GIC
in MStar/SigmaStar Armv7 SoCs.
All of the chips so far have two instances of this
controller.
One instance controls what are called "IRQ" interrupts
by the vendor code I have seen.
The other instance controls what are called "FIQ" interrupts
by the vendor code. Presumably because they can be FIQ
interrupts. Right now the FIQ bypass is disabled in the
GIC so they operate just the same as the IRQ interrupts.
The register layouts are the same for both. The FIQ one
needs to have the status bit cleared on EOI so that difference
is handled by a compatible string difference.
I initially made this an RFC because this is my first
interrupt controller driver and I expect to have made a
bunch of mistakes. I've cleaned this up a bit since then
but I still expect it's not 100% correct. Especially
the offset to map the INTC interrupt to the GIC interrupt.
Daniel Palmer (3):
dt: bindings: interrupt-controller: Add binding description for
msc313-intc
irqchip: mstar: msc313-intc interrupt controller driver
ARM: mstar: Add interrupt controller to base dtsi
.../mstar,msc313-intc.yaml | 79 +++++++
MAINTAINERS | 2 +
arch/arm/boot/dts/mstar-v7.dtsi | 20 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-msc313-intc.c | 210 ++++++++++++++++++
5 files changed, 312 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mstar,msc313-intc.yaml
create mode 100644 drivers/irqchip/irq-msc313-intc.c
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2.27.0
