Add the IRQ and FIQ intc instances to the base MStar/SigmaStar v7
dtsi. All of the known SoCs have both and at the same place with
their common IPs using the same interrupt lines.
Signed-off-by: Daniel Palmer <daniel@xxxxxxxx>
Tested-by: Willy Tarreau <w@xxxxxx>
---
arch/arm/boot/dts/mstar-v7.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi
index 3b7b9b793736..2b3bb0886d1a 100644
--- a/arch/arm/boot/dts/mstar-v7.dtsi
+++ b/arch/arm/boot/dts/mstar-v7.dtsi
@@ -85,6 +85,26 @@ reboot {
mask = <0x79>;
};
+ intc_fiq: intc@201310 {
+ compatible = "mstar,msc313-intc-fiq";
+ interrupt-controller;
+ reg = <0x201310 0x40>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ mstar,gic-offset = <96>;
+ mstar,nr-interrupts = <32>;
+ };
+
+ intc_irq: intc@201350 {
+ compatible = "mstar,msc313-intc-irq";
+ interrupt-controller;
+ reg = <0x201350 0x40>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ mstar,gic-offset = <32>;
+ mstar,nr-interrupts = <64>;
+ };
+
l3bridge: l3bridge@204400 {
compatible = "mstar,l3bridge";
reg = <0x204400 0x200>;
--
2.27.0
