On Fri, 31 Jul 2020 23:08:22 +0300, Serge Semin wrote: > Each DW DMA controller channel can be synthesized with different > parameters like maximum burst-length, multi-block support, maximum data > width, etc. Most of these parameters determine the DW DMAC channels > performance in its own aspect. On the other hand these parameters can > be implicitly responsible for the channels performance degradation > (for instance multi-block support is a very useful feature, but having > it disabled during the DW DMAC synthesize will provide a more optimized > core). Since DMA slave devices may have critical dependency on the DMA > engine performance, let's provide a way for the slave devices to have > the DMA-channels allocated from a pool of the channels, which according > to the system engineer fulfill their performance requirements. > > The pool is determined by a mask optionally specified in the fifth > DMA-cell of the DMA DT-property. If the fifth cell is omitted from the > phandle arguments or the mask is zero, then the allocation will be > performed from a set of all channels provided by the DMA controller. > > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> > --- > .../devicetree/bindings/dma/snps,dma-spear1340.yaml | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
