On 2020-07-28 10:18, Grzegorz Jaszczyk wrote:
From: Suman Anna <s-anna@xxxxxx>
The PRUSS INTC has a fixed number of output interrupt lines that are
connected to a number of processors or other PRUSS instances or other
devices (like DMA) on the SoC. The output interrupt lines 2 through 9
are usually connected to the main Arm host processor and are referred
to as host interrupts 0 through 7 from ARM/MPU perspective.
All of these 8 host interrupts are not always exclusively connected
to the Arm interrupt controller. Some SoCs have some interrupt lines
not connected to the Arm interrupt controller at all, while a few
others
have the interrupt lines connected to multiple processors in which they
need to be partitioned as per SoC integration needs. For example,
AM437x
and 66AK2G SoCs have 2 PRUSS instances each and have the host interrupt
5
connected to the other PRUSS, while AM335x has host interrupt 0 shared
between MPU and TSC_ADC and host interrupts 6 & 7 shared between MPU
and
a DMA controller.
Add logic to the PRUSS INTC driver to ignore both these shared and
invalid interrupts.
Signed-off-by: Suman Anna <s-anna@xxxxxx>
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@xxxxxxxxxx>
---
v3->v4:
- Due to changes in DT bindings which converts irqs-reserved
property from uint8-array to bitmask requested by Rob introduce
relevant changes in the driver.
- Merge the irqs-reserved and irqs-shared to one property since they
can be handled by one logic (relevant change was introduced to DT
binding).
This isn't what I asked for in my initial review.
I repeatedly asked for the *handling* to be common, not for the
properties to be merged. I don't mind either way, but I understood
there were two properties for a good reason. Has this reason gone?
Anyway, I'll come back to it once I start reviewing the series
again.
M.
--
Jazz is not dead. It just smells funny...
