Arnd Bergmann writes: > On Mon, Jun 15, 2020 at 3:33 PM Lars Povlsen <lars.povlsen@xxxxxxxxxxxxx> wrote: >> >> This patch series adds support for Microchip Sparx5 SoC, the CPU >> system of a advanced, TSN capable gigabit switch. The CPU is an armv8 >> x 2 CPU core (A53). >> >> Although this is an ARM core, it shares some peripherals with the >> Microsemi Ocelot MIPS SoC. > > I've picked up this version of the series into an arm/newsoc branch in > the soc tree, > except for the pinctrl patch that Linus Walleij already merged. > Great! Thanks a lot for following up! > I see you still have a few pending patches for other subsystems (spi, mmc) > and I'm not sure what the status is for those and am dropping them for the > moment. > Yes, I had a question out for the SPI maintainer but did not get any feedback, so I was thinking just doing my own assumptions and refreshing the series - probably tomorrow. I also just bumped the MMC maintainer (Adrian) yesterday, as he did send a me an 'Acked-by', but it hasn't been merged it seems. > Once the bindings are accepted by the respective subsystem maintainers, > please send any remaining DT patches as a follow-up to what I've already > merged. > I'll try to work out the puzzle, might need to reach out directly to to determine whats missing. Later, ---Lars > Arnd -- Lars Povlsen, Microchip
