On Mon, Jun 15, 2020 at 3:33 PM Lars Povlsen <lars.povlsen@xxxxxxxxxxxxx> wrote:
>
> This patch series adds support for Microchip Sparx5 SoC, the CPU
> system of a advanced, TSN capable gigabit switch. The CPU is an armv8
> x 2 CPU core (A53).
>
> Although this is an ARM core, it shares some peripherals with the
> Microsemi Ocelot MIPS SoC.
I've picked up this version of the series into an arm/newsoc branch in
the soc tree,
except for the pinctrl patch that Linus Walleij already merged.
I see you still have a few pending patches for other subsystems (spi, mmc)
and I'm not sure what the status is for those and am dropping them for the
moment.
Once the bindings are accepted by the respective subsystem maintainers,
please send any remaining DT patches as a follow-up to what I've already
merged.
Arnd
