On Tue, Jul 14, 2020 at 03:28:30PM +0200, Arnd Bergmann wrote:
> On Tue, Jul 14, 2020 at 2:58 PM Serge Semin
> <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> wrote:
> >
> > config MIPS_CDMM
> > bool "MIPS Common Device Memory Map (CDMM) Driver"
> > - depends on CPU_MIPSR2
> > + depends on CPU_MIPSR2 || CPU_MIPSR5
> > help
>
> Wouldn't a kernel built for P5600 have CPU_MIPSR2 set already?
No. P5600 core is based on MIPS32 r5, for which since 5.8 there has been a
dedicated kernel config CPU_MIPSR5 available.
> I thought R5 was just a backwards-compatible extension of R2.
Yes, it's an extension and they are compatible in most of aspects, but
there are still differences, which when activated/used make kernel built
for R5 being incompatible with R2. For instance there is an ISA
extension in R5 which hasn't been available in R5 like "eretnc"
(return from exceptions with no atomic flag cleared), "mfhc/mthc0"
(extended C0 register move instructions), etc. There is some other
features/optimizations available since R5. Please see commit
ab7c01fdc3cf ("mips: Add MIPS Release 5 support") for details.
>
> If not, what about R3?
Currently if some chip is equipped with R3, then the kernel must be built
for R2 with features like EVA enabled if it's required.
-Sergey
>
> Arnd
