Hi Andy, thank you so much for your time and attention. See below.
On Sun, Jul 5, 2020 at 10:45 AM Andy Duan <fugang.duan@xxxxxxx> wrote:
>
> Don't consider it complex, GPR5[9] just select the rgmii gtx source from PAD or internal
> Like：
> GPR5[9] is cleared: PAD -> MAC gtx
> GPR5[9] is set: Pll_enet -> MAC gtx
> As you said, register one clock mux for the selection, assign the clock parent by board dts
> file, but now current clock driver doesn't support GPR clock.
Ok, so for imx6q plus only, we create two new clocks (MAC_GTX and PAD)
and a new clock mux, controlled by GPR5[9]:
enet_ref-o------>ext>---pad------| \
| |M |----mac_gtx
o-----------------------|_/
Where M = mux controlled by GPR5[9]
clk_mac_gtx -> clk_pad -> clk_enet_ref is the default. when a board
wants internal routing, it can just do:
&fec {
assigned-clocks = <&clks IMX6QDL_CLK_MAC_GTX>;
assigned-clock-parents = <&clks IMX6QDL_CLK_ENET_REF>;
};
But, how do we manage clk_pad? It is routed externally, and can be
connected to:
- enet_ref (typically via GPIO_16)
- an external oscillator
- an external PHY clock
ext phy---------| \
| |
enet_ref-o------|M |----pad------| \
| |_/ | |
| |M |----mac_gtx
| | |
o-----------------------|_/
How do we tell the clock framework that clk_pad has a mux that can
be connected to _any_ external clock? and also enet_ref?
