Hi Sven,
On Thu, Jul 2, 2020 at 2:53 PM Sven Van Asbroeck <thesven73@xxxxxxxxx> wrote:
> + /*
> + * On imx6 plus, enet_ref from ANATOP/CCM can be internally routed to
> + * be the PTP clock source, instead of having to be routed through
> + * pads.
> + */
> + if (of_machine_is_compatible("fsl,imx6qp")) {
> + clksel = of_property_read_bool(np, "fsl,ptpclk-bypass-pad") ?
> + IMX6Q_GPR5_ENET_TXCLK_SEL_PLL :
> + IMX6Q_GPR5_ENET_TXCLK_SEL_PAD;
> + regmap_update_bits(gpr, IOMUXC_GPR5,
> + IMX6Q_GPR5_ENET_TXCLK_SEL_MASK, clksel);
> + }
With the device tree approach, I think that a better place to touch
GPR5 would be inside the fec driver.
You can refer to drivers/pci/controller/dwc/pci-imx6.c and follow the
same approach for accessing the GPR register:
...
/* Grab GPR config register range */
imx6_pcie->iomuxc_gpr =
syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr")
For the property name, what about fsl,txclk-from-pll?
