This patchset adds mt6779 iommu support.
mt6779 has two iommus, they are MM_IOMMU(M4U) and APU_IOMMU which used ARM Short-Descriptor translation format.
The mt6779's MM_IOMMU-SMI and APU_IOMMU HW diagram is as below, it is only a brief diagram:
EMI
|
--------------------------------------
| |
MM_IOMMU APU_IOMMU
| |
SMI_COMMOM----------- APU_BUS
| | |
SMI_LARB(0~11) | |
| | |
| | --------------
| | | | |
Multimedia engine CCU VPU MDLA EMDA
All the connections are hardware fixed, software can not adjust it.
Compared with mt8183, SMI_BUS_ID width has changed from 10 to 12. SMI Larb number is described in bit[11:7],
Port number is described in bit[6:2]. In addition, there are some registers has changed in mt6779, so we need
to redefine and reuse them.
The patchset only used MM_IOMMU, so we only add MM_IOMMU basic function, such as smi_larb port definition, registers
definition and hardware initialization.
change notes:
v6:
1. Fix build error for "PATCH v5 02/10".
2. Use more precise definitions and commit messages.
v5:
1. Split "iommu/mediatek: Add mt6779 IOMMU basic support(patch v4)" to three patches(from PATCH v5 08/10 to PATCH v5 10/10).
2. Use macro definitions to replace bool values in mtk_iommu_plat_data structure
http://lists.infradead.org/pipermail/linux-mediatek/2020-June/013586.html
v4:
1. Rebase on v5.8-rc1.
2. Fix coding style.
3. Add F_MMU_IN_DRDER_WR_EN definition in MISC_CTRL to improve performance.
https://lkml.org/lkml/2020/6/16/1741
v3:
1. Rebase on v5.7-rc1.
2. Remove unused port definition,ex:APU and CCU port in mt6779-larb-port.h.
3. Remove "change single domain to multiple domain" part(from PATCH v2 09/19 to PATCH v2 19/19).
4. Redesign mt6779 basic part
(1)Add some register definition and reuse them.
(2)Redesign smi larb bus ID to analyze IOMMU translation fault.
(3)Only init MM_IOMMU and not use APU_IOMMU.
http://lists.infradead.org/pipermail/linux-mediatek/2020-May/029811.html
v2:
1. Rebase on v5.5-rc1.
2. Delete M4U_PORT_UNKNOWN define because of not use it.
3. Correct coding format.
4. Rename offset=0x48 register.
5. Split "iommu/mediatek: Add mt6779 IOMMU basic support(patch v1)" to several patches(patch v2).
http://lists.infradead.org/pipermail/linux-mediatek/2020-January/026131.html
v1:
http://lists.infradead.org/pipermail/linux-mediatek/2019-November/024567.html
Chao Hao (10):
dt-bindings: mediatek: Add bindings for MT6779
iommu/mediatek: Rename the register STANDARD_AXI_MODE(0x48) to MISC_CTRL
iommu/mediatek: Use a u32 flags to describe different HW features
iommu/mediatek: Setting MISC_CTRL register
iommu/mediatek: Move inv_sel_reg into the plat_data
iommu/mediatek: Add sub_comm id in translation fault
iommu/mediatek: Add REG_MMU_WR_LEN_CTRL register definition
iommu/mediatek: Extend protect pa alignment value
iommu/mediatek: Modify MMU_CTRL register setting
iommu/mediatek: Add mt6779 basic support
.../bindings/iommu/mediatek,iommu.txt | 2 +
drivers/iommu/mtk_iommu.c | 110 +++++++---
drivers/iommu/mtk_iommu.h | 20 +-
include/dt-bindings/memory/mt6779-larb-port.h | 206 ++++++++++++++++++
4 files changed, 299 insertions(+), 39 deletions(-)
--
2.18.0
