Re: [PATCH 2/2] clk: bcm63xx-gate: add BCM6318 support

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On 6/10/2020 1:29 AM, Philippe Mathieu-Daudé wrote:
> Hi,
> 
> On Wed, Jun 10, 2020 at 8:13 AM Álvaro Fernández Rojas
> <noltari@xxxxxxxxx> wrote:
>>
>> Hi Florian,
>>
>>> El 10 jun 2020, a las 4:27, Florian Fainelli <f.fainelli@xxxxxxxxx> escribió:
>>>
>>>
>>>
>>> On 6/9/2020 4:30 AM, Álvaro Fernández Rojas wrote:
>>>> +static const struct clk_bcm63xx_table_entry bcm6318_clocks[] = {
>>>> +    { .name = "adsl_asb", .bit = 0, },
>>>> +    { .name = "usb_asb", .bit = 1, },
>>>> +    { .name = "mips_asb", .bit = 2, },
>>>> +    { .name = "pcie_asb", .bit = 3, },
>>>> +    { .name = "phymips_asb", .bit = 4, },
>>>> +    { .name = "robosw_asb", .bit = 5, },
>>>> +    { .name = "sar_asb", .bit = 6, },
>>>> +    { .name = "sdr_asb", .bit = 7, },
>>>> +    { .name = "swreg_asb", .bit = 8, },
>>>> +    { .name = "periph_asb", .bit = 9, },
>>>> +    { .name = "cpubus160", .bit = 10, },
>>>> +    { .name = "adsl", .bit = 11, },
>>>> +    { .name = "sar124", .bit = 12, },
>>>
>>> Nit: this should be sar125
>>
>> Nice catch, I will fix this in v2.
>>
>>>
>>>> +    { .name = "mips", .bit = 13, .flags = CLK_IS_CRITICAL, },
>>>> +    { .name = "pcie", .bit = 14, },
>>>> +    { .name = "robosw250", .bit = 16, },
>>>> +    { .name = "robosw025", .bit = 17, },
>>>> +    { .name = "sdr", .bit = 19, .flags = CLK_IS_CRITICAL, },
>>>> +    { .name = "usb", .bit = 20, },
>>>
>>> This should probably be "usbd" to indicate this is the USB device clock
>>> (not host)
>>
>> Ok, I will change it. I got confused by the fact that both (usbd and usbh) were present on 6318_map_part.h:
>> #define USBD_CLK_EN         (1 << 20)
>> #define USBH_CLK_EN         (1 << 20)
> 
> Is there a datasheet to verify that?

Not a public one, but I can confirm this is correct given the internal
datasheet.
-- 
Florian



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