On Tue, Jun 09, 2020 at 02:55:35PM +0200, Sascha Hauer wrote: > On Mon, Jun 08, 2020 at 04:57:37PM +0200, Andrew Lunn wrote: > > On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote: > > > The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode > > > called DRSGMII. > > > > > > This patch adds a corresponding phy-mode string 'drsgmii' and parses it > > > from DT. The MVNETA then configures the SERDES protocol value > > > accordingly. > > > > > > It was successfully tested on a MV78460 connected to a FPGA. > > > > Hi Sascha > > > > Is this really overclocked SGMII, or 2500BaseX? How does it differ > > from 2500BaseX, which mvneta already supports? > > I think it is overclocked SGMII or 2500BaseX depending on the Port MAC > Control Register0 PortType setting bit. > As said to Russell we have a fixed link so nobody really cares if it's > SGMII or 2500BaseX. This boils down the patch to fixing the Serdes > configuration setting for 2500BaseX. Hi Sascha Does 2500BaseX work for your use case? Since this drsmgii mode is not well defined, i would prefer to not add it, unless it is really needed. Andrew
