The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode called DRSGMII. This patch adds a corresponding phy-mode string 'drsgmii' and parses it from DT. The MVNETA then configures the SERDES protocol value accordingly. It was successfully tested on a MV78460 connected to a FPGA. Signed-off-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx> --- .../devicetree/bindings/net/ethernet-controller.yaml | 1 + drivers/net/ethernet/marvell/mvneta.c | 7 ++++++- include/linux/phy.h | 3 +++ 3 files changed, 10 insertions(+), 1 deletion(-) This patch has already been sent 3 years ago here: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170123142206.5390-1-jlu@xxxxxxxxxxxxxx/ Since then the driver has evolved a lot. 2.5Gbps is properly configured in the MAC now. diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index ac471b60ed6ae..4eead3c89bd3e 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -66,6 +66,7 @@ properties: - gmii - sgmii - qsgmii + - drsgmii - tbi - rev-mii - rmii diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 51889770958d8..807c698576c74 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -109,6 +109,7 @@ #define MVNETA_SERDES_CFG 0x24A0 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 #define MVNETA_QSGMII_SERDES_PROTO 0x0667 +#define MVNETA_DRSGMII_SERDES_PROTO 0x1107 #define MVNETA_TYPE_PRIO 0x24bc #define MVNETA_FORCE_UNI BIT(21) #define MVNETA_TXQ_CMD_1 0x24e4 @@ -3734,10 +3735,11 @@ static void mvneta_validate(struct phylink_config *config, struct mvneta_port *pp = netdev_priv(ndev); __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; - /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ + /* We only support QSGMII, SGMII, DRSGMII, 802.3z and RGMII modes */ if (state->interface != PHY_INTERFACE_MODE_NA && state->interface != PHY_INTERFACE_MODE_QSGMII && state->interface != PHY_INTERFACE_MODE_SGMII && + state->interface != PHY_INTERFACE_MODE_DRSGMII && !phy_interface_mode_is_8023z(state->interface) && !phy_interface_mode_is_rgmii(state->interface)) { bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); @@ -3851,6 +3853,7 @@ static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, if (state->interface == PHY_INTERFACE_MODE_QSGMII || state->interface == PHY_INTERFACE_MODE_SGMII || + state->interface == PHY_INTERFACE_MODE_DRSGMII || phy_interface_mode_is_8023z(state->interface)) new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; @@ -4968,6 +4971,8 @@ static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) else if (phy_mode == PHY_INTERFACE_MODE_SGMII || phy_interface_mode_is_8023z(phy_mode)) mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); + else if (phy_mode == PHY_INTERFACE_MODE_DRSGMII) + mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_DRSGMII_SERDES_PROTO); else if (!phy_interface_mode_is_rgmii(phy_mode)) return -EINVAL; diff --git a/include/linux/phy.h b/include/linux/phy.h index 2432ca463ddc0..bf3276b330f9e 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -109,6 +109,7 @@ typedef enum { PHY_INTERFACE_MODE_USXGMII, /* 10GBASE-KR - with Clause 73 AN */ PHY_INTERFACE_MODE_10GKR, + PHY_INTERFACE_MODE_DRSGMII, PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -190,6 +191,8 @@ static inline const char *phy_modes(phy_interface_t interface) return "usxgmii"; case PHY_INTERFACE_MODE_10GKR: return "10gbase-kr"; + case PHY_INTERFACE_MODE_DRSGMII: + return "drsgmii"; default: return "unknown"; } -- 2.27.0
