On Mon, Jun 08, 2020 at 05:08:01PM +0100, Russell King - ARM Linux admin wrote: > On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote: > > The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode > > called DRSGMII. > > > > This patch adds a corresponding phy-mode string 'drsgmii' and parses it > > from DT. The MVNETA then configures the SERDES protocol value > > accordingly. > > > > It was successfully tested on a MV78460 connected to a FPGA. > > Digging around, this is Armada XP? Which SoCs is this mode supported? > There's no mention of DRSGMII in the A38x nor A37xx documentation which > are later than Armada XP. It's an Armada XP MV78460 in my case. I have no idea what other SoCs this mode is supported on. > > What exactly is "drsgmii"? It can't be "double-rate" SGMII because that > would give you 2Gbps max instead of the 1Gbps, but this gives 2.5Gbps, > so I'm really not sure using "drsgmii" is a good idea. It may be what > Marvell call it, but we really need to know if there's some vendor > neutral way to refer to it. The abbreviation really is for "Double Rated SGMII". It seems it has 2.5 times the clock rate than ordinary SGMII. Another term I found is HSGMII (High serial gigabit media-independent interface) which also has 2.5Gbps. Anyway, I just learned from the paragraph you added to Documentation/networking/phy.rst that 1000BASEX differs from SGMII in the format of the control word. As we have a fixed link to a FPGA the control word seems to be unused, at least the Port MAC Control Register0 PortType setting bit doesn't change anything. So I can equally well use the existing 2500BASEX mode. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
