Add DT bindings YAML schema for PWM controller driver of Lightning Mountain(LGM) SoC. Signed-off-by: Rahul Tanwar <rahul.tanwar@xxxxxxxxxxxxxxx> --- .../devicetree/bindings/pwm/pwm-intel-lgm.yaml | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-intel-lgm.yaml diff --git a/Documentation/devicetree/bindings/pwm/pwm-intel-lgm.yaml b/Documentation/devicetree/bindings/pwm/pwm-intel-lgm.yaml new file mode 100644 index 000000000000..adb33265aa5e --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-intel-lgm.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-intel-lgm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LGM SoC PWM controller + +maintainers: + - Rahul Tanwar <rahul.tanwar@xxxxxxxxx> + +properties: + compatible: + const: intel,lgm-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 2 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - resets + +examples: + - | + pwm: pwm@e0d00000 { + compatible = "intel,lgm-pwm"; + reg = <0xe0d00000 0x30>; + #pwm-cells = <2>; + clocks = <&cgu0 126>; + resets = <&rcu0 0x30 21>; + }; -- 2.11.0
