mfgcfg clock is under MFG_ASYNC power domain Signed-off-by: Weiyi Lu <weiyi.lu@xxxxxxxxxxxx> --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index ff7fe0c..911f0db 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -707,6 +707,7 @@ compatible = "mediatek,mt8183-mfgcfg", "syscon"; reg = <0 0x13000000 0 0x1000>; #clock-cells = <1>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_ASYNC>; }; mmsys: syscon@14000000 { -- 1.8.1.1.dirty