On Monday 18. May 2020 13.26.58 Paul Cercueil wrote: > >> > >> @@ -186,13 +186,16 @@ static void > >> > >> ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, > >> > >> regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, > >> JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16, > >> JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16); > >> > >> + > >> + regmap_write(priv->map, JZ_REG_LCD_IPUR, JZ_LCD_IPUR_IPUREN > >> + (ht * vpe / 3) << JZ_LCD_IPUR_IPUR_LSB); > > > > This hunk also indicates that it may be better to merge the IPU within > > the existing driver. > > This writes the IPUR register of the CRTC, nothing wrong here. Since I noticed it in the above patch details, I think the mask when updating the burst setting in the LCD_CTRL register should - in general - involve multiple bits, since the BST field is 3 bits wide on the JZ4780 and 2 bits wide on earlier products. Just setting BURST_16 (0b10) could potentially enable BURST_32 (0b11) or other field values that are not explicitly defined. Hope this is useful! Paul
