On Mon, May 18, 2020 at 09:26:59AM -0600, Rob Herring wrote: > On Fri, May 08, 2020 at 12:36:20PM +0300, Serge Semin wrote: > > Baikal-T1 Boot SPI is a part of the SoC System Controller and is > > responsible for the system bootup from an external SPI flash. It's a DW > > APB SSI-based SPI-controller with no interrupts, no DMA, with just one > > native chip-select available and a single reference clock. Since Baikal-T1 > > SoC is normally booted up from an external SPI flash this SPI controller > > in most of the cases is supposed to be connected to a single SPI-nor > > flash. Additionally in order to provide a transparent from CPU point of > > view initial code execution procedure the system designers created an IP > > block which physically maps the SPI flash found at CS0 to a memory region. BTW Rob, could you also provide your review for the next patch: https://lore.kernel.org/linux-mips/20200515104758.6934-20-Sergey.Semin@xxxxxxxxxxxxxxxxxxxx/ ? We agreed with Mark to merge this driver into the generic DW APB SSI code so to be available for another platforms. Since our DW APB SSI IP's got too many peculiarities I'll have to provide a new compatible string. It would be great to add it into the DW schema binding instead of currently available text-based legacy binding file. [nip]
