On Fri, May 15, 2020 at 01:53:13PM +0300, Andy Shevchenko wrote: > On Fri, May 15, 2020 at 11:46:01AM +0530, Vinod Koul wrote: > > On 12-05-20, 15:35, Andy Shevchenko wrote: > > > On Tue, May 12, 2020 at 12:16:22AM +0300, Serge Semin wrote: > > > > On Fri, May 08, 2020 at 02:21:52PM +0300, Andy Shevchenko wrote: > > > > > On Fri, May 08, 2020 at 01:53:01PM +0300, Serge Semin wrote: > > ... > > > > My point here that we probably can avoid complications till we have real > > > hardware where it's different. As I said I don't remember a such, except > > > *maybe* Intel Medfield, which is quite outdated and not supported for wider > > > audience anyway. > > > > IIRC Intel Medfield has couple of dma controller instances each one with > > different parameters *but* each instance has same channel configuration. > > That's my memory too. > > > I do not recall seeing that we have synthesis parameters per channel > > basis... But I maybe wrong, it's been a while. > > Exactly, that's why I think we better simplify things till we will have real > issue with it. I.o.w. no need to solve the problem which doesn't exist. Ok then. My hardware is also synthesized with uniform max block size parameter. I'll remove that maximum of maximum search pattern and use the block size found for the very first channel to set the maximum segment size parameter. -Sergey > > -- > With Best Regards, > Andy Shevchenko > >
