On Tue, May 12, 2020 at 12:16:22AM +0300, Serge Semin wrote: > On Fri, May 08, 2020 at 02:21:52PM +0300, Andy Shevchenko wrote: > > On Fri, May 08, 2020 at 01:53:01PM +0300, Serge Semin wrote: > > > Maximum block size DW DMAC configuration corresponds to the max segment > > > size DMA parameter in the DMA core subsystem notation. Lets set it with a > > > value specific to the probed DW DMA controller. It shall help the DMA > > > clients to create size-optimized SG-list items for the controller. This in > > > turn will cause less dw_desc allocations, less LLP reinitializations, > > > better DMA device performance. > > Yeah, I have locally something like this and I didn't dare to upstream because > > there is an issue. We have this information per DMA controller, while we > > actually need this on per DMA channel basis. > > > > Above will work only for synthesized DMA with all channels having same block > > size. That's why above conditional is not needed anyway. > > Hm, I don't really see why the conditional isn't needed and this won't work. As > you can see in the loop above Initially I find a maximum of all channels maximum > block sizes and use it then as a max segment size parameter for the whole device. > If the DW DMA controller has the same max block size of all channels, then it > will be found. If the channels've been synthesized with different block sizes, > then the optimization will work for the one with greatest block size. The SG > list entries of the channels with lesser max block size will be split up > by the DW DMAC driver, which would have been done anyway without > max_segment_size being set. Here we at least provide the optimization for the > channels with greatest max block size. > > I do understand that it would be good to have this parameter setup on per generic > DMA channel descriptor basis. But DMA core and device descriptor doesn't provide > such facility, so setting at least some justified value is a good idea. > > > > > OTOH, I never saw the DesignWare DMA to be synthesized differently (I remember > > that Intel Medfield has interesting settings, but I don't remember if DMA > > channels are different inside the same controller). > > > > Vineet, do you have any information that Synopsys customers synthesized DMA > > controllers with different channel characteristics inside one DMA IP? > > AFAICS the DW DMAC channels can be synthesized with different max block size. > The IP core supports such configuration. So we can't assume that such DMAC > release can't be found in a real hardware just because we've never seen one. > No matter what Vineet will have to say in response to your question. My point here that we probably can avoid complications till we have real hardware where it's different. As I said I don't remember a such, except *maybe* Intel Medfield, which is quite outdated and not supported for wider audience anyway. -- With Best Regards, Andy Shevchenko
