On Wed, May 13, 2020 at 06:46:14PM +0800, Ramuthevar,Vadivel MuruganX wrote: > From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> > > Add YAML file for dt-bindings to support NAND Flash Controller > on Intel's Lightning Mountain SoC. > > Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> > --- > .../devicetree/bindings/mtd/intel,lgm-nand.yaml | 83 ++++++++++++++++++++++ > 1 file changed, 83 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml > > diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml > new file mode 100644 > index 000000000000..d9e0df8553fa > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml > @@ -0,0 +1,83 @@ > +# SPDX-License-Identifier: GPL-2.0 Dual license new bindings please: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Intel LGM SoC NAND Controller Device Tree Bindings > + > +allOf: > + - $ref: "nand-controller.yaml" > + > +maintainers: > + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> > + > +properties: > + compatible: > + const: intel,lgm-nand-controller > + > + reg: > + maxItems: 1 Looks like you have 4 or 6 entries, not 1. Need to define what each one is. > + > + clocks: > + maxItems: 1 > + > + dmas: > + maxItems: 2 > + > + dma-names: > + enum: > + - rx > + - tx This defines a single entry. I believe you want: items: - const: tx - const: rx > + > + pinctrl-names: true No need for this. Tools add pinctrl properties. > + > +patternProperties: > + "^nand@[a-f0-9]+$": > + type: object > + properties: > + reg: > + minimum: 0 > + maximum: 7 > + > + nand-ecc-mode: true > + > + nand-ecc-algo: > + const: hw > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - dmas > + > +additionalProperties: false > + > +examples: > + - | > + nand-controller@e0f00000 { > + compatible = "intel,nand-controller"; Doesn't match the schema. > + reg = <0xe0f00000 0x100>, > + <0xe1000000 0x300>, > + <0xe1400000 0x8000>, > + <0xe1c00000 0x1000>; Is it 4 or 6 entries? > + reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1", > + "addr_sel0","addr_sel1"; Not documented. > + clocks = <&cgu0 125>; > + dma-names = "tx", "rx"; > + #address-cells = <1>; > + #size-cells = <0>; > + #clock-cells = <1>; This is a clock provider too? > + > + nand@0 { > + reg = <0>; > + nand-on-flash-bbt; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > + }; > + > +... > -- > 2.11.0 >
