This adds DT bindings for the Microsemi SGPIO controller, bindings mscc,ocelot-sgpio and mscc,luton-sgpio. Reviewed-by: Alexandre Belloni <alexandre.belloni@xxxxxxxxxxx> Signed-off-by: Lars Povlsen <lars.povlsen@xxxxxxxxxxxxx> --- .../bindings/pinctrl/mscc,ocelot-sgpio.yaml | 66 +++++++++++++++++++ MAINTAINERS | 1 + include/dt-bindings/gpio/mchp-sgpio.h | 21 ++++++ 3 files changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-sgpio.yaml create mode 100644 include/dt-bindings/gpio/mchp-sgpio.h diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-sgpio.yaml new file mode 100644 index 0000000000000..a332a0f4582fa --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-sgpio.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-sgpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi Serial GPIO controller + +maintainers: + - Lars Povlsen <lars.povlsen@xxxxxxxxxxxxx> + +description: | + By using a serial interface, the SIO controller significantly extend + the number of available GPIOs with a minimum number of additional + pins on the device. The primary purpose of the SIO controllers is to + connect control signals from SFP modules and to act as an LED + controller. + +properties: + $nodename: + pattern: "gpio" + + compatible: + enum: + - mscc,ocelot-sgpio + - mscc,luton-sgpio + + clocks: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + microchip,sgpio-ports: + description: This is a 32-bit bitmask, configuring whether a + particular port in the controller is enabled or not. This allows + unused ports to be removed from the bitstream and reduce latency. + $ref: "/schemas/types.yaml#/definitions/uint32" + +required: + - compatible + - clocks + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +examples: + - | + sgpio0: gpio@61101036c { + compatible = "mscc,ocelot-sgpio"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio0_pins>; + pinctrl-names = "default"; + reg = <0x1101036c 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 64 64>; + microchip,sgpio-ports = <0x00ffffff>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index de64fd4548697..cdb63ca04670d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11233,6 +11233,7 @@ S: Supported F: Documentation/devicetree/bindings/mips/mscc.txt F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt F: Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml +F: Documentation/devicetree/bindings/pinctrl/mscc,ocelot-sgpio.yaml F: arch/mips/boot/dts/mscc/ F: arch/mips/configs/generic/board-ocelot.config F: arch/mips/generic/board-ocelot.c diff --git a/include/dt-bindings/gpio/mchp-sgpio.h b/include/dt-bindings/gpio/mchp-sgpio.h new file mode 100644 index 0000000000000..0736158563f0a --- /dev/null +++ b/include/dt-bindings/gpio/mchp-sgpio.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * This header provides constants for binding mscc,*-sgpio + * + * The first cell in the SGPIO specifier is the GPIO ID. The macros below + * provide machros for this. + * + * The second cell contains standard flag values specified in gpio.h. + */ + +#ifndef _DT_BINDINGS_GPIO_MSCC_SGPIO_H +#define _DT_BINDINGS_GPIO_MSCC_SGPIO_H + +#include <dt-bindings/gpio/gpio.h> + +#define MSCC_SGPIOS_PER_BANK 32 +#define MSCC_SGPIO_BANK_DEPTH 4 + +#define MSCC_SGPIO(port, bit) ((bit * MSCC_SGPIOS_PER_BANK) + port) + +#endif -- 2.26.2
