Hi Martin, On Sat, 28 Mar 2020 at 06:04, Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> wrote: > > The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC > card interface with 1/4/8-bit bus width. > It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock). > > The public S805 datasheet [0] contains a short documentation about the > registers. Unfortunately it does not describe how to use the registers > to make the hardware work. Thus this driver is based on reading (and > understanding) the Amlogic 3.10 GPL kernel code. > > Some hardware details are not easy to see. Jianxin Pan was kind enough > to answer my questions: > The hardware has built-in busy timeout support. The maximum timeout is > 30 seconds. This is only documented in Amlogic's internal > documentation. > > The controller only works with very specific clock configurations. The > details are not part of the public datasheet. In my own words the > supported configurations are: > - 399.812kHz: clkin = 850MHz div = 2126 sd_rx_phase = 63 > - 1MHz: clkin = 850MHz div = 850 sd_rx_phase = 55 > - 5.986MHz: clkin = 850MHz div = 142 sd_rx_phase = 24 > - 25MHz: clkin = 850MHz div = 34 sd_rx_phase = 15 > - 47.222MHz: clkin = 850MHz div = 18 sd_rx_phase = 11/15 (SDR50/HS) > - 53.125MHz: clkin = 850MHz div = 16 sd_rx_phase = (tuning) > - 70.833MHz: clkin = 850MHz div = 12 sd_rx_phase = (tuning) > - 85MHz: clkin = 850MHz div = 10 sd_rx_phase = (tuning) > - 94.44MHz: clkin = 850MHz div = 9 sd_rx_phase = (tuning) > - 106.25MHz: clkin = 850MHz div = 8 sd_rx_phase = (tuning) > - 127.5MHz: clkin = 1275MHz div = 10 sd_rx_phase = (tuning) > - 141.667MHz: clkin = 850MHz div = 6 sd_rx_phase = (tuning) > - 159.375MHz: clkin = 1275MHz div = 8 sd_rx_phase = (tuning) > - 212.5MHz: clkin = 1275MHz div = 6 sd_rx_phase = (tuning) > - (sd_tx_phase is always 1, 94.44MHz is not listed in the datasheet > but this is what the 3.10 BSP kernel on Odroid-C1 actually uses) > > NOTE: CMD23 support is disabled for now because it results in command > timeouts and thus decreases read performance. > > Tested-by: Wei Wang <lnykww@xxxxxxxxx> > Tested-by: Xin Yin <yinxin_1989@xxxxxxxxxx> > Reviewed-by: Xin Yin <yinxin_1989@xxxxxxxxxx> > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> > --- Please add my tested on Odroid C1+ Tested-by: Anand Moon <linux.amoon@xxxxxxxxx> Best Regards -Anand
