Quoting Guenter Roeck (2020-04-06 12:30:50) > On Mon, Mar 09, 2020 at 08:42:41PM +0100, Lubomir Rintel wrote: > > The clk-of-mmp2 driver pretends that the clock outputs from the PLLs are > > constant, but in fact they are configurable. > > > > Add logic for obtaining the actual clock rates on MMP2 as well as MMP3. > > There is no documentation for either SoC, but the "systemsetting" drivers > > from Marvell GPL code dump provide some clue as far as MPMU registers on > > MMP2 [1] and MMP3 [2] go. > > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp2_systemsetting.c > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp3-dell-ariel.git/tree/drivers/char/mmp3_systemsetting.c > > > > A separate commit will adjust the clk-of-mmp2 driver. > > > > Tested on a MMP3-based Dell Wyse 3020 as well as MMP2-based OLPC > > XO-1.75 laptop. > > > > Signed-off-by: Lubomir Rintel <lkundrak@xxxxx> > > This patch results in: > > arm-linux-gnueabi-ld: drivers/clk/mmp/clk.o: in function `mmp_register_pll_clks': > drivers/clk/mmp/clk.c:192: undefined reference to `mmp_clk_register_pll' > > when building arm:pxa910_defconfig. > Thanks. I see that Arnd has sent a fix for this. https://lore.kernel.org/r/20200408160518.2798571-1-arnd@xxxxxxxx
