On 05/15/2014 10:49 PM, Thierry Reding wrote: > On Thu, May 15, 2014 at 06:30:13PM +0200, Arnd Bergmann wrote: >> On Thursday 15 May 2014 15:56:03 Michal Simek wrote: >>> IP is configurable as is normal for us. >>> You can select IP with just one timer. >>> It means register locations for specific timer are fixed. >>> http://www.xilinx.com/support/documentation/ip_documentation/xps_timer.pdf >>> >>> timer0 - offset 0x0 >>> timer1 - offset 0x10 (doesn't need to be synthesized) >>> >>> There is one interrupt for both timers. >>> >>> Timers can be as timers (up/down count/ reload with or without IRQs) >>> But then one options is to use both timers and generate PWM signal. >>> From full ip description in DT you can see xlnx,gen0-assert = <1>; >>> which can suggest that this IP can output PMW signal. >>> (We can also detect if PWM0 signal is connected just to be sure >>> that PWM can be enabled). >>> >>> There is also capture trigger mode where external signal start/stop >>> timer counting. >>> >>> It means there are 3 modes - timer, capture and PWM. >>> Timer (clocksource, clockevent) requires specific handling, >>> PWM has own subsystem and not sure if there is any subsystem for >>> capture mode. Is there any? >> >> I don't think so. Possibly somewhere in IIO. > > I think so too. There was a patch set not so long ago that added PWM > capture support for one of the TI PWM controllers to IIO. It is probably this. https://lwn.net/Articles/583998/ https://lkml.org/lkml/2014/2/5/378 There were some comments in v3 which haven't been fixed. Matt: What's the status on this? Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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