Hi Rabeeh and Baruch
On Sun, Mar 29, 2020 at 11:42:35AM +0300, Rabeeh Khoury wrote:
> On Sun, Mar 29, 2020 at 9:22 AM Baruch Siach <baruch@xxxxxxxxxx> wrote:
> >
> > Hi Stefan,
> >
> > On Sun, Mar 29 2020, eichest@xxxxxxxxx wrote:
> > > From: Stefan Eichenberger <eichest@xxxxxxxxx>
> > >
> > > According to the ClearFog-GT-8K-rev-1_1-Simplified-Schematic the reset
> > > pin for the gigabit phy is MPP62 and not MPP43.
> >
> > Have you tested that on real hardware?
> >
> > The 1Gb PHY reset on my Clearfog GT-8K is connected to MPP43. Russell's
> > commit 46f94c7818e7 ("arm64: dts: clearfog-gt-8k: set gigabit PHY reset
> > deassert delay") indicates that this is the case on his board as well.
> >
> > In case there was a hardware change between board revisions, we need
> > another dtb for that revision.
>
> It's a bug in the simplified schematics since that schematics is based
> on rev 1.0 and not rev 1.1 as claimed.
>
> In rev 1.0; the 1Gbps phy reset was connected to MPP62; but that MPP
> is not functional as a GPIO when selecting MPP[56:61] as SD card.
> Due to that we manually rewired ALL rev 1.0 PCBs 1Gbps phy to be
> connected to MPP43 via R8038 pads.
>
> Rev 1.1 fixes this by that by disconnecting 1Gbps phy reset from MPP62
> and wiring it to MPP43.
> So basically rev 1.0 and rev 1.1 are compatible software wise. We will
> fix the schematics.
Ahh now I see, I didn't enable the phy driver when I did the test with
the default devicetree and then when I changed the devicetree I also
enabled the driver, that's my fault.
Sorry for the confusion... I can confirm that it works with MPP43.
Thanks for the clarification!
Regards,
Stefan
