Hi, On 11/03/2020 08:18, Jitao Shi wrote: > Some chips's sample mode are rising, falling and dual edge (both > falling and rising edge). > Extern the pclk-sample property to support dual edge. > > Acked-by: Rob Herring <robh@xxxxxxxxxx> > Reviewed-by: CK Hu <ck.hu@xxxxxxxxxxxx> > Signed-off-by: Jitao Shi <jitao.shi@xxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/media/video-interfaces.txt | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt > index f884ada0bffc..da9ad24935db 100644 > --- a/Documentation/devicetree/bindings/media/video-interfaces.txt > +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt > @@ -118,8 +118,8 @@ Optional endpoint properties > - data-enable-active: similar to HSYNC and VSYNC, specifies the data enable > signal polarity. > - field-even-active: field signal level during the even field data transmission. > -- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock > - signal. > +- pclk-sample: sample data on rising (1), falling (0) or both rising and > + falling (2) edge of the pixel clock signal. > - sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for > LOW/HIGH respectively. > - data-lanes: an array of physical data lane indexes. Position of an entry > This changes the bus format, but we recently introduced a bus format negociation between bridges to avoid adding such properties into DT, and make bus format setup dynamic between an encoder and a bridge. It would be great to use that instead. Neil
