Copy&paste suggested an MMIO pattern that wasn't there, so the wrong
MMIO base addresses for SPI2 and SPI3 sneaked in.
Fix them, now double checked against the manual and similar SoCs.
Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes")
Reported-by: JuanEsf <juanesf91@xxxxxxxxx>
---
arch/arm/boot/dts/sun8i-r40.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 8f09a24b36ec..8c4c4282a055 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -679,10 +679,10 @@
#size-cells = <0>;
};
- spi2: spi@1c07000 {
+ spi2: spi@1c17000 {
compatible = "allwinner,sun8i-r40-spi",
"allwinner,sun8i-h3-spi";
- reg = <0x01c07000 0x1000>;
+ reg = <0x01c17000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
clock-names = "ahb", "mod";
@@ -692,10 +692,10 @@
#size-cells = <0>;
};
- spi3: spi@1c0f000 {
+ spi3: spi@1c1f000 {
compatible = "allwinner,sun8i-r40-spi",
"allwinner,sun8i-h3-spi";
- reg = <0x01c0f000 0x1000>;
+ reg = <0x01c1f000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
clock-names = "ahb", "mod";
--
2.14.5
