Hi, This is version 2 of the patchset to add clock driver to the Agilex platform. It's been while since I posted v1 so I want clarify the patches a bit in this cover letter. Since the Agilex clocking is very similar to Stratix10, the driver is very similar and will re-use the clock data structures of Stratix10. Thus, there needs to be updates to the Stratix10 clock driver. Patch 1/3 : update the Stratix10 clock driver to make use of the new parent data scheme Patch 2/3 : version 2 of the documenation, converted to YAML Patch 3/4 : version 2 of the clock driver with comments from v1 addressed Thanks, Dinh Dinh Nguyen (3): clk: socfpga: stratix10: use new parent data scheme dt-bindings: documentation: add clock bindings information for Agilex clk: socfpga: agilex: add clock driver for the Agilex platform .../bindings/clock/intc,agilex.yaml | 79 ++++ drivers/clk/Makefile | 1 + drivers/clk/socfpga/Makefile | 2 + drivers/clk/socfpga/clk-agilex.c | 369 ++++++++++++++++++ drivers/clk/socfpga/clk-gate-s10.c | 5 +- drivers/clk/socfpga/clk-periph-s10.c | 10 +- drivers/clk/socfpga/clk-pll-s10.c | 74 +++- drivers/clk/socfpga/clk-s10.c | 110 ++++-- drivers/clk/socfpga/stratix10-clk.h | 10 +- include/dt-bindings/clock/agilex-clock.h | 70 ++++ 10 files changed, 689 insertions(+), 41 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/intc,agilex.yaml create mode 100644 drivers/clk/socfpga/clk-agilex.c create mode 100644 include/dt-bindings/clock/agilex-clock.h -- 2.17.1
