On Thu, 27 Feb 2020 16:44:25 +0000 Mark Brown <broonie@xxxxxxxxxx> wrote: > On Thu, Feb 27, 2020 at 05:40:31PM +0100, Geert Uytterhoeven wrote: > > On Thu, Feb 27, 2020 at 5:28 PM Mark Brown <broonie@xxxxxxxxxx> wrote: > > > > It's what we do for other properties, and if this is anything like the > > > other things adding extra wiring you can't assume that the ability to > > > use the feature for TX implies RX. > > > Double Transfer Rate uses the same wire. > > But is it still on either the TX or RX signals? There's no separate RX/TX pins when using xD-xD-xD modes (pins switch from RX to TX) and I doubt DTR will ever be used on single SPI. > > > But as you sample at both the rising and the falling edges of the clock, this > > makes the cpha setting meaningless for such transfers, I think ;-) > > Might affect what the first bit is possibly? > > > However, as the future may bring us QDR, perhaps this should not be a > > boolean flag, but an integer value? > > Cfr. spi-tx-bus-width vs. the original spi-tx-dual/spi-tx-quad proposal. > > > What would be a good name (as we only need one)? spi-data-phases? > > Sounds reasonable, apart from the increasingly vague connection with > something that's recognizably SPI :P Or maybe we should refrain from adding a new flag and wait a bit to see if this DTR mode is actually used for regular SPI transfers (AKA not spi-mem) :-).
