On Sat, 22 Feb 2020 14:03:55 +0200, Grygorii Strashko wrote: > TI AM654x/J721E SoCs have the same PHY interface selection mechanism for > CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields > placement is different. > > This patch adds corresponding compatible strings to enable support for TI > AM654x/J721E SoCs. > > Signed-off-by: Grygorii Strashko <grygorii.strashko@xxxxxx> > --- > Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@xxxxxxxxxx>
