These patches add new edac driver for Cadence ddr memory controller. Cadence controller detects single(CE) and double(UE) bit errors during memory operations(RMW). DDR controller raised the interrupt on detection of the ecc error event and fill the data into registers. Driver handle the interrupt event and notify edac subsystem about ecc errors. The patch series has two patches: 1. Add driver support into edac subsystem 2. Add devicetree binding in yaml format Dhananjay Kangude (2): EDAC/Cadence:Add EDAC driver for cadence memory controller dt-bindings: edac: Add cadence ddr mc support .../devicetree/bindings/edac/cdns,ddr-edac.yaml | 56 ++ drivers/edac/Kconfig | 7 + drivers/edac/Makefile | 1 + drivers/edac/cadence_edac.c | 615 ++++++++++++++++++++ 4 files changed, 679 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/edac/cdns,ddr-edac.yaml create mode 100644 drivers/edac/cadence_edac.c
