From: Peng Fan <peng.fan@xxxxxxx>
Sorry to bind the mailbox/firmware patch together. This is make it
to understand what changed to support using 1 TX and 1 RX channel
for SCFW message.
Per i.MX8QXP Reference mannual, there are several message using
examples. One of them is:
Passing short messages: Transmit register(s) can be used to pass
short messages from one to four words in length. For example,
when a four-word message is desired, only one of the registers
needs to have its corresponding interrupt enable bit set at the
receiver side.
This patchset is to using this for SCFW message to replace four TX
and four RX method.
Pachset based on i.MX Shawn's for-next branch, commit fd7eba9fa1f534b710.
To test this patchset, I applied the below diff:
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index fb5f752b15fe..c5636624726e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -140,17 +140,11 @@
scu {
compatible = "fsl,imx-scu";
- mbox-names = "tx0", "tx1", "tx2", "tx3",
- "rx0", "rx1", "rx2", "rx3",
+ mbox-names = "tx0",
+ "rx0",
"gip3";
mboxes = <&lsio_mu1 0 0
- &lsio_mu1 0 1
- &lsio_mu1 0 2
- &lsio_mu1 0 3
&lsio_mu1 1 0
- &lsio_mu1 1 1
- &lsio_mu1 1 2
- &lsio_mu1 1 3
&lsio_mu1 3 3>;
clk: clock-controller {
@@ -546,6 +540,7 @@
reg = <0x5d1c0000 0x10000>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
+ fsl,scu;
};
lsio_mu2: mailbox@5d1d0000 {
Peng Fan (3):
dt-bindings: mailbox: imx-mu: add fsl,scu property
mailbox: imx: support SCU channel type
firmware: imx-scu: Support one TX and one RX
.../devicetree/bindings/mailbox/fsl,mu.txt | 1 +
drivers/firmware/imx/imx-scu.c | 54 +++++++++++++++++-----
drivers/mailbox/imx-mailbox.c | 42 +++++++++++++++--
3 files changed, 82 insertions(+), 15 deletions(-)
base-commit: fd7eba9fa1f534b7102f4762e25c991f78ec283d
--
2.16.4
