Hi, please consider applying this patch series. Its goal is to ultimately provide accurate clock sources from PLLs configured by firmware on MMP2 and MMP3. Currently they are hardcoded to more or less wrong values, which causes bad timings when they are use (e.g. to generate display clock). It starts off with a handful of cleanups: [PATCH 01/10] clk: mmp2: Remove a unused prototype [PATCH 02/10] clk: mmp2: Constify some strings [PATCH 03/10] dt-bindings: clock: Convert marvell,mmp2-clock to The next patch adds the logic for calculating the rate of clock signals coming from the PLLs dynamically, while not actually switching the driver over to using it. [PATCH 04/10] clk: mmp2: Add support for PLL clock sources Then MMP2 is switched over: [PATCH 05/10] clk: mmp2: Stop pretending PLL outputs are constant Switching MMP3 requires some more work, because until now, the driver has been the same for both versions of the SoC: [PATCH 06/10] dt-bindings: clock: Add MMP3 compatible string [PATCH 07/10] clk: mmp2: Check for MMP3 [PATCH 08/10] dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs [PATCH 09/10] clk: mmp2: Add PLLs that are available on MMP3 [PATCH 10/10] ARM: dts: mmp3: Use the MMP3 compatible string for The hardware vendor doesn't supply documentation, so this is best-effort work based on the code dump from Marvell. Tested on MMP2 and MMP3 based hardware I have; details in relevant commit messages. Thank you, Lubo
