Quoting Taniya Das (2020-02-11 04:13:55)
> The clock disable signal for video_cc_vcodec0_core_clk is tied to
> vcodec0_gdsc which is supported in the HW control mode. Thus turning off
> the clock would be taken care automatically when the GDSC turns OFF by
> hardware and clock driver does not require to poll on the CLK_OFF bit.
>
> Signed-off-by: Taniya Das <tdas@xxxxxxxxxxxxxx>
> ---
> drivers/clk/qcom/videocc-sc7180.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c
> index c363c3c..276e5ec 100644
> --- a/drivers/clk/qcom/videocc-sc7180.c
> +++ b/drivers/clk/qcom/videocc-sc7180.c
> @@ -97,7 +97,7 @@ static struct clk_branch video_cc_vcodec0_axi_clk = {
>
> static struct clk_branch video_cc_vcodec0_core_clk = {
> .halt_reg = 0x890,
> - .halt_check = BRANCH_HALT,
> + .halt_check = BRANCH_HALT_VOTED,
Ok. I looked closely and now I notice that some code is using
BRANCH_VOTED and other code is using BRANCH_HALT_VOTED. In the end, it's
the same value. I guess I should remove BRANCH_VOTED from the header
file and make it BIT(7) that's ored in there so that everyone
consistently uses BRANCH_HALT_VOTED.
> .clkr = {
> .enable_reg = 0x890,
