On Tue, Jan 21, 2020 at 11:12:11PM +0300, Dmitry Osipenko wrote: > 21.01.2020 18:54, Thierry Reding пишет: > > On Tue, Jan 21, 2020 at 05:18:43PM +0200, Georgi Djakov wrote: > >> On 1/21/20 16:10, Thierry Reding wrote: [...] > >>> I'm not sure if that TEGRA_ICC_EMEM makes a lot of sense. It's always > >>> going to be the same and it's arbitrarily defined, so it's effectively > >>> useless. But other than that it looks good. > >> > >> Well, in most cases the target would be the EMEM, so that's fine. I have seen > >> that other vendors that may have an additional internal memory, especially > >> dedicated to some DSPs and in such cases the bandwidth needs are different for > >> the two paths (to internal memory and DDR). > > > > Most chips have a small internal memory that can be used, though it > > seldomly is. However, in that case I would expect the target to be a > > completely different device, so it'd look more like this: > > > > interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &iram>, > > ...; > > > > I don't think EMEM has any "downstream" other than external memory. > > The node ID should be mandatory in terms of interconnect, even if it's a > single node. EMC (provider) != EMEM (endpoint). I don't understand why. An ID only makes sense if you've got multiple endpoints. For example, a regulator is a provider with a single endpoint so we don't specify an ID. By its very definition an ID is used to identify something and we use it with a phandle to create a unique pair that identifies a resource within whatever the phandle represents, with the goal to differentiate it from other resources within the same provider. However, if there's only one such resource, the ID becomes redundant because the phandle without an ID is already unique and there's no need to differentiate with an extra ID. Thierry
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