On Tue, Jan 14, 2020 at 01:18:01PM +0100, Michal Simek wrote: > Hi Alvaro, > > here is missing description. Ok, I'll put something once we've finished reviewing this. Given the comments below, maybe is it better do split this in qspi+smcc changes and maybe leter on work on the rest of the issues? > On 14. 01. 20 13:00, Alvaro Gamez Machado wrote: > > Signed-off-by: Alvaro Gamez Machado <alvaro.gamez@xxxxxxxxxx> > > --- > > arch/arm/boot/dts/zynq-7000.dtsi | 50 ++++++++++++++++++++++++++++++-- > > 1 file changed, 47 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi > > index ca6425ad794c..8358315d7803 100644 > > --- a/arch/arm/boot/dts/zynq-7000.dtsi > > +++ b/arch/arm/boot/dts/zynq-7000.dtsi > > @@ -197,6 +197,45 @@ spi1: spi@e0007000 { > > #size-cells = <0>; > > }; > > > > + qspi: spi@e000d000 { > > + clock-names = "ref_clk", "pclk"; > > + clocks = <&clkc 10>, <&clkc 43>; > > + compatible = "xlnx,zynq-qspi-1.0"; > > + status = "disabled"; > > + interrupt-parent = <&intc>; > > + interrupts = <0 19 4>; > > + reg = <0xe000d000 0x1000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + smcc: memory-controller@e000e000 { > > + #address-cells = <1>; > > + #size-cells = <1>; > > + status = "disabled"; > > + clock-names = "memclk", "apb_pclk"; > > + clocks = <&clkc 11>, <&clkc 44>; > > + compatible = "arm,pl353-smc-r2p1", "arm,primecell"; > > + interrupt-parent = <&intc>; > > + interrupts = <0 18 4>; > > + ranges ; > > + reg = <0xe000e000 0x1000>; > > + nand0: flash@e1000000 { > > + status = "disabled"; > > + compatible = "arm,pl353-nand-r2p1"; > > note: Driver is not in mainline but dt binding has been reviewed already. Ok, so I understand we can leave this as is, even though it won't fully work, but at least the hardware gets defined, is that right? > > > + reg = <0xe1000000 0x1000000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + }; > > + nor0: flash@e2000000 { > > + status = "disabled"; > > + compatible = "cfi-flash"; > > + reg = <0xe2000000 0x2000000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + }; > > + }; > > + > > gem0: ethernet@e000b000 { > > compatible = "cdns,zynq-gem", "cdns,gem"; > > reg = <0xe000b000 0x1000>; > > @@ -297,14 +336,19 @@ dmac_s: dmac@f8003000 { > > > > devcfg: devcfg@f8007000 { > > compatible = "xlnx,zynq-devcfg-1.0"; > > - reg = <0xf8007000 0x100>; > > interrupt-parent = <&intc>; > > interrupts = <0 8 4>; > > - clocks = <&clkc 12>; > > - clock-names = "ref_clk"; > > + reg = <0xf8007000 0x100>; > > + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; > > + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; > > This is not the part of dt binding. Sorry, I don't understand what you mean by this. I'm simply adding the list of clocks that the PS can provide to the PL region of the zynq. Is this wrong? > > syscon = <&slcr>; > > }; > > > > + efuse: efuse@f800d000 { > > + compatible = "xlnx,zynq-efuse"; > > + reg = <0xf800d000 0x20>; > > + }; > > ditto. Ok, this came from Xilinx' tools and there's no driver for it, so I'll just remove it. > > + > > global_timer: timer@f8f00200 { > > compatible = "arm,cortex-a9-global-timer"; > > reg = <0xf8f00200 0x20>; > > > > > Thanks, > Michal Thanks! -- Alvaro G. M.