On Thu, Jan 02, 2020 at 01:26:56AM +0000, Andre Przywara wrote: > The ARM Cortex-A7 cores used in the Allwinner R40 SoC have their usual > Performance Monitoring Unit (PMU), which allows perf to use hardware > events. > The SoC integrator just needs to connect each per-core interrupt line > to the GIC. The R40 manual does not really mention those IRQ lines, but > experimentation in U-Boot shows that interrupts 152-155 are connected to > the four cores (similar to the A20). > > Tested on a Bananapi M2 Berry, with perf and taskset to confirm the > association between cores and interrupts. > > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx> Applied, thanks! Maxime
Attachment:
signature.asc
Description: PGP signature
