Re: [PATCH 03/14] media: sun4i-csi: Fix data sampling polarity handling

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On Mon, Dec 16, 2019 at 12:59:13AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@xxxxxxxx>
>
> The CLK_POL field specifies whether data is sampled on the falling or
> rising edge of PCLK, not whether the data lines are active high or low.
> Evidence of this can be found in the timing diagram labeled "horizontal
> size setting and pixel clock timing".
>
> Fix the setting by checking the correct flag, V4L2_MBUS_PCLK_SAMPLE_RISING.
> While at it, reorder the three polarity flag checks so HSYNC and VSYNC
> are grouped together.
>
> Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver")
> Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx>

Acked-by: Maxime Ripard <mripard@xxxxxxxxxx>

Thanks!
Maxime

Attachment: signature.asc
Description: PGP signature


[Index of Archives]     [Device Tree Compilter]     [Device Tree Spec]     [Linux Driver Backports]     [Video for Linux]     [Linux USB Devel]     [Linux PCI Devel]     [Linux Audio Users]     [Linux Kernel]     [Linux SCSI]     [XFree86]     [Yosemite Backpacking]


  Powered by Linux