Re: [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses

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Subject: Re: [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses
From: Bjorn Helgaas <helgaas@xxxxxxxxxx>
Date: Mon, 9 Dec 2019 15:15:54 -0600
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>, Rob Herring <robh+dt@xxxxxxxxxx>, Arnd Bergmann <arnd@xxxxxxxx>, Andrew Murray <andrew.murray@xxxxxxx>, linux-pci@xxxxxxxxxxxxxxx, devicetree@xxxxxxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx, linux-omap@xxxxxxxxxxxxxxx
In-reply-to: <20191209092147.22901-6-kishon@ti.com>
User-agent: Mutt/1.10.1 (2018-07-13)

On Mon, Dec 09, 2019 at 02:51:39PM +0530, Kishon Vijay Abraham I wrote:
> Certain platforms like TI's J721E allow only 32-bit register accesses.
> Add read and write accessors to perform only 32-bit accesses in order to
> support platfroms like TI's J721E.

s/platfroms/platforms/

References:
- [PATCH 05/13] PCI: cadence: Add read and write accessors to perform only 32-bit accesses
  - From: Kishon Vijay Abraham I

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