On Fri, Nov 22, 2019 at 11:45:01PM +0200, Leonard Crestez wrote: > DRAM frequency switches are executed in firmware and can change the > configuration of the DRAM PLL outside linux. Mark these CLKs with > CLK_GET_RATE_NOCACHE so we always read back the PLL config registers and > recalculate rates. > > In current DRAM frequency tables on 8mm/8mn only the maximum frequency > uses the PLL so it's always configured in the same way. However reading > back the PLL configuration is the correct behavior and allows additional > setpoints in the future. > > Signed-off-by: Leonard Crestez <leonard.crestez@xxxxxxx> > Reviewed-by: Abel Vesa <abel.vesa@xxxxxxx> Applied, thanks.
