The SPIBSC-0 clock is marked as critical because for XIP systems, this
is the SPI flash controller it will boot from and the kernel will also
be running from so it cannot be turned off.
Signed-off-by: Chris Brandt <chris.brandt@xxxxxxxxxxx>
---
arch/arm/boot/dts/r7s72100.dtsi | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index d03dcd919d6f..a422bbe872bc 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -101,6 +101,26 @@
#size-cells = <1>;
ranges;
+ spibsc0: spi@3fefa000 {
+ compatible = "renesas,r7s72100-spibsc", "renesas,spibsc";
+ reg = <0x3fefa000 0x100>, <0x18000000 0x4000000>;
+ clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
+ power-domains = <&cpg_clocks>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spibsc1: spi@3fefb000 {
+ compatible = "renesas,r7s72100-spibsc", "renesas,spibsc";
+ reg = <0x3fefb000 0x100>, <0x1c000000 0x4000000>;
+ clocks = <&mstp9_clks R7S72100_CLK_SPIBSC1>;
+ power-domains = <&cpg_clocks>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
L2: cache-controller@3ffff000 {
compatible = "arm,pl310-cache";
reg = <0x3ffff000 0x1000>;
@@ -467,11 +487,13 @@
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0438 4>;
- clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
+ clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>, <&b_clk>, <&b_clk>;
clock-indices = <
R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
+ R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1
>;
- clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
+ clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3", "spibsc0", "spibsc1";
+ clock-critical = <4>; /* spibsc0 */
};
mstp10_clks: mstp10_clks@fcfe043c {
--
2.23.0
