On Tue, Nov 26, 2019 at 12:43:19PM +0100, Ard Biesheuvel wrote:
> Add a DT description of the CPU and cache hierarchy as found on
> the AMD Seattle SOC. Given the tight coupling of the PMU with
> the CPUs, move the PMU node into the cpu .dtsi file as well, and
> add the missing affinity description.
[...]
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
This should be "arm,cortex-a57"; likewise for the other CPUs.
> + pmu {
> + compatible = "arm,armv8-pmuv3";
And this should be (and should have been) "arm,cortex-a57-pmu".
> + interrupts = <0x0 0x7 0x4>,
> + <0x0 0x8 0x4>,
> + <0x0 0x9 0x4>,
> + <0x0 0xa 0x4>,
> + <0x0 0xb 0x4>,
> + <0x0 0xc 0x4>,
> + <0x0 0xd 0x4>,
> + <0x0 0xe 0x4>;
> + interrupt-affinity = <&CPU0>,
> + <&CPU1>,
> + <&CPU2>,
> + <&CPU3>,
> + <&CPU4>,
> + <&CPU5>,
> + <&CPU6>,
> + <&CPU7>;
> + };
> +};
Otherwise, this looks good to me.
Thanks,
Mark.
