On 11/13/19 6:50 AM, Leonard Crestez wrote: > Add devicetree bindings for the i.MX DDR Controller on imx8m series > chips. It supports dynamic frequency switching between multiple data > rates and this is exposed to Linux via the devfreq subsystem. > > Signed-off-by: Leonard Crestez <leonard.crestez@xxxxxxx> > --- > .../memory-controllers/fsl/imx8m-ddrc.yaml | 57 +++++++++++++++++++ > 1 file changed, 57 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml > > diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml > new file mode 100644 > index 000000000000..7c98e3509f75 > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml > @@ -0,0 +1,57 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: i.MX8M DDR Controller > + > +maintainers: > + - Leonard Crestez <leonard.crestez@xxxxxxx> > + > +properties: > + compatible: > + items: > + - enum: > + - fsl,imx8mn-ddrc > + - fsl,imx8mm-ddrc > + - fsl,imx8mq-ddrc > + - const: fsl,imx8m-ddrc > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 4 > + > + clock-names: > + items: > + - const: core > + - const: pll > + - const: alt > + - const: apb > + > + operating-points-v2: true > + opp-table: true > + > +required: > + - reg > + - compatible > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/imx8mm-clock.h> > + ddrc: memory-controller@3d400000 { > + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; > + reg = <0x3d400000 0x400000>; The probe() function doesn't get the IORESOURCE_MEM from dt? Is it needed? > + clock-names = "core", "pll", "alt", "apb"; > + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, > + <&clk IMX8MM_DRAM_PLL>, > + <&clk IMX8MM_CLK_DRAM_ALT>, > + <&clk IMX8MM_CLK_DRAM_APB>; > + operating-points-v2 = <&ddrc_opp_table>; > + }; > -- Best Regards, Chanwoo Choi Samsung Electronics
