This adds support for dynamic scaling of the DDR Controller (ddrc) present in imx8m series. Actual frequency switching is implemented inside TF-A, this driver wraps the SMC calls and synchronizes the clk tree. DRAM frequency switching requires clock manipulation but during this operation DRAM itself is briefly inaccessible so this operation is performed a SMC call to by TF-A which runs from a SRAM area. Upon returning to linux the clock tree is updated to correspond to hardware configuration. This is handled via CLK_GET_RATE_NO_CACHE for dividers but muxes are handled manually: the driver will prepare/enable the new parents ahead of switching (so that the expected roots are enabled) and afterwards it will call clk_set_parent to ensure the parents in clock framework are up-to-date. This series is atomically useful and roughly similar to devfreq drivers for tegra and rockchip. Running at lower dram rates saves power but can affect the functionality of other blocks in the chip (display, vpu etc). Support for in-kernel constraints will some separately. Angus/Martin: You previously attempted to test on purism boards, this updated version should work without hacks and has no dependencies. Changes since v4: * Restore empty _get_dev_status: testing shows this is *NOT* optional. If absent then switching to simple_ondemand governor will trigger an Oops. * Keep clk registration on single-line in clk-imx8m* for consistency with rest of the file. * Drop explicit "select PM_OPP" * Check for NULL new_dram_core_parent * Rename "out_dis_" labels to out_disable_* * Use dev_warn on imx8m_ddrc_set_freq error paths after SMC call (where operation is not abandoned). * More elaborate error messages in imx8m_ddrc_target * More elaborate checks when fetching clks in imx8m_ddrc_set_freq * Rename ddrc nodes to memory-controller@* as per devicetree.org "Generic Names Recommendation" * Collect reviews * Defer perf support Link to v4: https://patchwork.kernel.org/cover/11235685/ Changes since v3: * Rename to imx8m-ddrc. Similar blocks are present on imx7d and imx8qxp/imx8qm but soc integration is different. * Move dt bindings to /memory-controllers/fsl/ * Fix dt validation issues * Fix imx8mm.dtsi ddrc referencing ddrc_opp_table which is only defined in evk * Move opps to child of ddrc device node * Only add imx_ddrc_get_dev_status in perf patch. * Adjust print messages Link to v3: https://patchwork.kernel.org/cover/11221935/ Changes since v2: * Add support for entire imx8m family including imx8mq B0. * Also mark dram PLLs as CLK_GET_RATE_NO_CACHE (required for imx8mq b0 low OPP) * Explicitly update dram pll rate at the end of imx_ddrc_set_freq. * Use do_div in imx-ddrc (kbuild robot) * Improve explanations around adding CLK_GET_RATE_NO_CACHE to dram clks. (Stephen Boyd) * Handle ddrc devfreq-events earlier for fewer probe defers. * Validate DDRC opp tables versus firmware: supported OPPs depend on board and SOC revision. * Move DDRC opp tables to board dts because they can vary based on ram type on board. * Verify DDRC rate is changed in clk tree and otherwise report an error. * Change imx_ddrc_freq.rate to be measure in MT/s and round down from HZ in imx_ddrc_find_freq instead. * Split away from NOC scaling and interconnect support. Link to v2: https://patchwork.kernel.org/cover/11104113/ Changes since v1: * bindings: Stop using "contains" for "compatible" * bindings: Set "additionalProperties: false" and document missing stuff. * Remove (c) from NXP copyright notice * Fix various checkpatch issues * Remove unused dram_alt_root clk from imx-ddrc Link to v1: https://patchwork.kernel.org/cover/11090649/ Changes since RFC v3: * Implement passive support and set NOC's parent to DDRC * Drop scaling AHB/AXI for now (NOC/DDRC use most power anyway) * Stop relying on clk_min_rate * Split into two devreq drivers (and bindings) because the ddrc is really a distinct piece of hardware. * Perform DRAM frequency inside devfreq instead of clk, mostly due to objections to earlier RFCs for imx8m-dram-clk. * Fetch info about dram clk parents from firmware instead of hardcoding in driver. This can more easily support additional rates. * Link: https://patchwork.kernel.org/cover/11056779/ * Link: https://patchwork.kernel.org/patch/11049429/ Scaling buses can cause problems for devices with realtime bandwith requirements such as display, the intention is to use the interconnect framework to make DEV_PM_QOS_MIN_FREQUENCY to devfreq. There are separate patches for that: * https://patchwork.kernel.org/cover/11104055/ * https://patchwork.kernel.org/cover/11078671/ Leonard Crestez (5): clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE dt-bindings: memory: Add bindings for imx8m ddr controller PM / devfreq: Add dynamic scaling for imx8m ddr controller arm64: dts: imx8m: Add ddr controller nodes .../memory-controllers/fsl/imx8m-ddrc.yaml | 57 +++ arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 18 + arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 + .../boot/dts/freescale/imx8mn-ddr4-evk.dts | 18 + arch/arm64/boot/dts/freescale/imx8mn.dtsi | 10 + arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 24 + arch/arm64/boot/dts/freescale/imx8mq.dtsi | 10 + drivers/clk/imx/clk-imx8mm.c | 11 +- drivers/clk/imx/clk-imx8mn.c | 12 +- drivers/clk/imx/clk-imx8mq.c | 12 +- drivers/clk/imx/clk-pll14xx.c | 7 + drivers/clk/imx/clk.h | 1 + drivers/devfreq/Kconfig | 9 + drivers/devfreq/Makefile | 1 + drivers/devfreq/imx8m-ddrc.c | 460 ++++++++++++++++++ 15 files changed, 650 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml create mode 100644 drivers/devfreq/imx8m-ddrc.c -- 2.17.1
