On Wed, Nov 06, 2019 at 10:07:48PM +0800, Chuanhong Guo wrote:
> update register descriptions and add an example binding using it.
>
> Signed-off-by: Chuanhong Guo <gch981213@xxxxxxxxx>
> ---
> .../devicetree/bindings/mtd/mtk-quadspi.txt | 21 ++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt
> index a12e3b5c495d..4860f6e96f5a 100644
> --- a/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt
> +++ b/Documentation/devicetree/bindings/mtd/mtk-quadspi.txt
> @@ -12,7 +12,10 @@ Required properties:
> "mediatek,mt7623-nor", "mediatek,mt8173-nor"
> "mediatek,mt7629-nor", "mediatek,mt8173-nor"
> "mediatek,mt8173-nor"
> -- reg: physical base address and length of the controller's register
> +- reg: Contains one or two entries, each of which is a tuple consisting of a
> + physical address and length. The first entry is the address and length
> + of the controller register set. The optional second entry is the address
> + and length of the area where the nor flash is mapped to.
All the compatibles support 2 entries? If not, which ones?
> - clocks: the phandle of the clocks needed by the nor controller
> - clock-names: the names of the clocks
> the clocks should be named "spi" and "sf". "spi" is used for spi bus,
> @@ -48,3 +51,19 @@ nor_flash: spi@1100d000 {
> };
> };
>
> +nor_flash: spi@11014000 {
> + compatible = "mediatek,mt7629-nor",
> + "mediatek,mt8173-nor";
> + reg = <0x11014000 0xe0>,
> + <0x30000000 0x10000000>;
> + clocks = <&pericfg CLK_PERI_FLASH_PD>,
> + <&topckgen CLK_TOP_FLASH_SEL>;
> + clock-names = "spi", "sf";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + };
> +};
> --
> 2.21.0
>
