Hi "Clément, I love your patch! Yet something to improve: [auto build test ERROR on sunxi/sunxi/for-next] [also build test ERROR on v5.4-rc5 next-20191031] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system. BTW, we also suggest to use '--base' option to specify the base tree in git format-patch, please see https://stackoverflow.com/a/37406982] url: https://github.com/0day-ci/linux/commits/Cl-ment-P-ron/Add-support-for-H6-PWM/20191104-043621 base: https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git sunxi/for-next config: mips-allmodconfig (attached as .config) compiler: mips-linux-gcc (GCC) 7.4.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree GCC_VERSION=7.4.0 make.cross ARCH=mips If you fix the issue, kindly add following tag Reported-by: kbuild test robot <lkp@xxxxxxxxx> All errors (new ones prefixed by >>): drivers//pwm/pwm-sun4i.c: In function 'sun4i_pwm_get_state': >> drivers//pwm/pwm-sun4i.c:132:6: error: 'data' undeclared (first use in this function); did you mean 'path'? data->has_direct_mod_clk_output) { ^~~~ path drivers//pwm/pwm-sun4i.c:132:6: note: each undeclared identifier is reported only once for each function it appears in vim +132 drivers//pwm/pwm-sun4i.c 112 113 static void sun4i_pwm_get_state(struct pwm_chip *chip, 114 struct pwm_device *pwm, 115 struct pwm_state *state) 116 { 117 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); 118 u64 clk_rate, tmp; 119 u32 val; 120 unsigned int prescaler; 121 122 clk_rate = clk_get_rate(sun4i_pwm->clk); 123 124 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); 125 126 /* 127 * PWM chapter in H6 manual has a diagram which explains that if bypass 128 * bit is set, no other setting has any meaning. Even more, experiment 129 * proved that also enable bit is ignored in this case. 130 */ 131 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > 132 data->has_direct_mod_clk_output) { 133 state->period = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, clk_rate); 134 state->duty_cycle = state->period / 2; 135 state->polarity = PWM_POLARITY_NORMAL; 136 state->enabled = true; 137 return; 138 } 139 140 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && 141 sun4i_pwm->data->has_prescaler_bypass) 142 prescaler = 1; 143 else 144 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; 145 146 if (prescaler == 0) 147 return; 148 149 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) 150 state->polarity = PWM_POLARITY_NORMAL; 151 else 152 state->polarity = PWM_POLARITY_INVERSED; 153 154 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == 155 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) 156 state->enabled = true; 157 else 158 state->enabled = false; 159 160 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); 161 162 tmp = prescaler * NSEC_PER_SEC * PWM_REG_DTY(val); 163 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 164 165 tmp = prescaler * NSEC_PER_SEC * PWM_REG_PRD(val); 166 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 167 } 168 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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